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19-2623; Rev 0; 1/03
KIT ATION EVALU ABLE AVAIL
1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers
General Description Features
o Operates from a 1.6V to 5.5V Supply (MAX1956) o 0.5% Output Accuracy o 0.8V to 0.9VIN Output Range o Up to 25A per Phase Output Current o On-Chip Boost Regulator Provides 5V Gate Drive o Up to 93% Efficiency o 180 Out-of-Phase Operation o 4% Voltage Margining o Lossless, Foldback Current Limit o Selectable Voltage Sequencing o Synchronizable to External Clock o Digital Soft-Start and Soft-Stop o Small 28-Pin, 5mm 5mm Thin QFN Package
MAX1955/MAX1956
The MAX1955/MAX1956 are dual-output, fixed-frequency, voltage-mode, pulse-width modulated (PWM) step-down controllers with 0.5% output accuracy. Each controller switches at a constant 600kHz and is 180 out-of-phase with the other controller, reducing input ripple current and the number of input capacitors. An on-chip bias supply generates a 5V gate drive to deliver up to 25A output current per phase with low-cost N-channel MOSFETs at up to 93% efficiency. Lossless adjustable current limit eliminates expensive currentsense resistors and improves efficiency. Foldback current limit reduces power dissipation during short-circuit conditions and handles transient overloads better than controllers using hiccup-mode short-circuit protection. Output voltage margining shifts output voltage by 4% from the nominal value to simplify system test. Outputs also can be powered up and down in selectable sequences to meet core and logic supply-rail requirements. The MAX1955/MAX1956 are available in a 28-lead thin QFN package with exposed pad.
Ordering Information
PART MAX1955ETI MAX1956ETI TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 28 Thin QFN-EP* 28 Thin QFN-EP*
Applications
Base Stations Telecom and Network Equipment Servers DSP, ASIC, P, and FPGA Supplies
INPUT 1.6V TO 5.5V
*EP = Exposed pad. Pin Configuration appears at end of data sheet.
Typical Operating Circuit
VDD
IN LXB BST1 OUTPUT 1 0.8V TO 0.9VIN UP TO 25A DH1 LX1
VDD BST2 DH2 LX2 MAX1956 OUTPUT 2 0.8V TO 0.9VIN UP TO 25A
DL2 FB2
DL1 PGND FB1 COMP1 SEQ GND SYNCHRONIZATION CLOCK ON/OFF VOLTAGE MARGINING ILIM1 SYNC EN ILIM2 AVDD VDD
COMP2 REF
________________________________________________________________ Maxim Integrated Products
1
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1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers MAX1955/MAX1956
ABSOLUTE MAXIMUM RATINGS
IN, AVDD, SYNC, EN, ILIM_, FB_, SEQ to GND.......-0.3V to +6V COMP_, REF to GND..............................-0.3V to (VAVDD + 0.3V) LXB to GND ..............................................-0.3V to (VVDD + 0.3V) DL_ to GND ...............................(VPGND - 0.3V) to (VVDD + 0.3V) BST_ to GND ..........................................................-0.3V to +12V DH1 to LX1 ...............................................-0.3V to (BST1 + 0.3V) DH2 to LX2 ...............................................-0.3V to (BST2 + 0.3V) LX1 to BST1..............................................................-6V to +0.3V LX2 to BST2..............................................................-6V to +0.3V PGND to GND or VDD to AVDD ............................-0.3V to +0.3V REF Short-Circuit to GND...........................................Continuous IVDD ...................................................................................250mA Continuous Power Dissipation* (TA = +70C) 28-Lead Thin QFN (derate 20.8mW/C above +70C)................................1667mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering 10s) ..................................+300C *Exposed pad soldered to PC board.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VEN = 3.3V; VVDD = VAVDD = 5V; VPGND = VGND = 0; CREF = 0.22F; SEQ = SYNC = GND; TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER IN Input Voltage Range IN Input Voltage UVLO FB Regulation Voltage FB Regulation Voltage with Positive Voltage Margining FB Regulation Voltage with Negative Voltage Margining Line Regulation Error Feedback Input Bias Feedback Transconductance COMP Source Current COMP Sink Current COMP Pulldown Resistance Output Soft-Start Time Step-Down Switching Frequency SYNC Frequency Range Maximum Duty Cycle Minimum Duty Cycle SYNC = GND (Note 3) 2 times step-down switching frequency Measured at DH_ Measured at DH_ 540 1080 90 93 7 In shutdown 4.27 600 660 1320 97 10 Percentage change from nominal regulation voltage Percentage change from nominal regulation voltage Note 2 -0.2 1 100 100 2 150 150 100 MAX1955 MAX1956 (Note 1) Rise or fall MAX1955, hysteresis = 35mV MAX1956, hysteresis = 30mV CONDITIONS MIN 2.25 1.6 1.9 1.30 0.796 3 -5 0.8 4 -4 0.1 TYP MAX 5.50 5.5 2.2 1.58 0.804 5 -3 0.3 +0.2 3 UNITS V V V % % % A mS A A ms kHz kHz % %
2
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1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VEN = 3.3V; VVDD = VAVDD = 5V; VPGND = VGND = 0; CREF = 0.22F; SEQ = SYNC = GND; TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER VDD No-Load Supply Current IN Supply Current IN Shutdown Supply Current REF Voltage REF Load Regulation Default Current-Limit Threshold Adjustable Current-Limit Threshold Thermal-Shutdown Threshold DH_ Gate-Driver On-Resistance DL_ Gate-Driver Pullup On-Resistance DL_ Gate-Driver Pulldown On-Resistance Dead Time (Adaptive) SYNC Minimum Pulse Width EN Voltage Range for Nominal Output Voltage EN Voltage Range for Positive Voltage Margining EN Voltage Range for Negative Voltage Margining EN Voltage Range for Shutdown EN, SEQ, SYNC Input High Voltage SEQ, SYNC Input Low Voltage EN, SEQ, SYNC Input Current BST_ Leakage Current in Shutdown VDD Output Voltage IVDD = 0 to 150mA -1 -20 4.75 IREF = -50A to +50A ILIM_ = VDD, measured from PGND to LX_ Measured from PGND to LX_ TJ rising, 15C hysteresis Pulling up or down DL_ high state DL_ low state DH_ falling to DL_ rising DL_ falling to DH_ rising High or low Percentage of VIN Percentage of VIN Percentage of VIN Percentage of VIN (Note 4) 200 80 55 30 0 VIN - 0.5 0.5 +1 +20 5.50 90 100 70 45 20 RILIM_ = 100k RILIM_ = 400k 127.5 60 240 150 75 300 160 1 1 0.35 23 26 1.8 1.8 0.65 1.267 1.28 CONDITIONS Total of VDD1 + VDD2 + AVDD current, SYNC = GND, no load on DH_ or DL_ MIN TYP 20 35 MAX 32 100 20 1.293 0.01 172.5 90 360 UNITS mA A A V V mV mV C ns ns % % % % V V A A V
MAX1955/MAX1956
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1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers MAX1955/MAX1956
ELECTRICAL CHARACTERISTICS
(VIN = VEN = 3.3V; VVDD = VAVDD = 5V; PGND = GND = 0; CREF = 0.22F; SYNC = GND; TA = -40C to +85C, unless otherwise noted.) (Note 5)
PARAMETER IN Input Voltage Range IN Input Voltage UVLO FB Regulation Voltage FB Regulation Voltage with Positive Voltage Margining FB Regulation Voltage with Negative Voltage Margining Line Regulation Error FB_ Input Bias Feedback Transconductance COMP_ Source Current COMP_ Sink Current COMP_ Pulldown Resistance Step-Down Switching Frequency SYNC Frequency Range Maximum Duty Cycle Minimum Duty Cycle VDD Quiescent Supply Current IN Quiescent Supply Current IN Shutdown Supply Current REF Voltage REF Load Regulation Default Current-Limit Threshold Adjustable Current-Limit Threshold IREF = -50A to +50A ILIM_ = VDD; measured from PGND to LX_ Measured from PGND to LX_ RILIM_ = 100k RILIM_ = 400k 127.5 60 240 1.267 In shutdown SYNC = GND (Note 3) 2 times step-down switching frequency Measured at DH_ Measured at DH_ Total of VDD1 + VDD2 + AVDD current, SYNC = GND, no load on DH_ or DL_ 540 1080 90 Percentage change from nominal regulation voltage Percentage change from nominal regulation voltage (Note 2) -0.2 1.0 100 100 100 660 1320 97 10 32 100 20 1.293 0.01 172.5 90 360 MAX1955 MAX1956 (Note 1) Rise or fall MAX1955 MAX1956 CONDITIONS MIN 2.25 1.6 1.9 1.30 0.794 +3 -5 TYP MAX 5.50 5.5 2.2 1.58 0.806 +5 -3 0.3 +0.2 3.1 UNITS V V V % % % A mS A A kHz kHz % % mA A A V V mV mV
4
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1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VEN = 3.3V; VVDD = VAVDD = 5V; PGND = GND = 0; CREF = 0.22F; SYNC = GND; TA = -40C to +85C, unless otherwise noted.) (Note 5)
PARAMETER DH_ Gate-Driver On-Resistance DL_ Gate-Driver Pullup On-Resistance DL_ Gate-Driver Pulldown On-Resistance SYNC Minimum Pulse Width EN Voltage Range for Nominal Output Voltage EN Voltage Range for Positive Voltage Margining EN Voltage Range for Negative Voltage Margining EN Voltage Range for Shutdown EN, SEQ, SYNC Input High Voltage SEQ, SYNC Input Low Voltage EN, SEQ, SYNC Input Current BST_ Leakage Current in Shutdown VDD Output Voltage IVDD = 0 to 150mA -1 -20 4.75 Pulling up or down DL_ high state DL_ low state High or low Percentage of VIN Percentage of VIN Percentage of VIN Percentage of VIN (Note 4) 200 80 55 30 0 VIN - 0.5 0.5 +1 +20 5.50 100 70 45 20 CONDITIONS MIN TYP MAX 1.8 1.8 0.65 UNITS ns % % % % V V A A V
MAX1955/MAX1956
Note 1: Note 2: Note 3: Note 4: Note 5:
IN input voltage must not drop below minimum voltage because of ripple or transient conditions. Guaranteed by design. Boost frequency is 2x step-down frequency. For proper startup, EN must exceed VIN - 0.5V. Specifications to -40C are guaranteed by design but not production tested.
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1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers MAX1955/MAX1956
Typical Operating Characteristics
(Circuit of Figure 5, TA = +25C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT WITH 3.3V INPUT
MAX1955/56 toc01
EFFICIENCY vs. LOAD CURRENT WITH 2.5V INPUT
MAX1955/56 toc02
MAX1956 EFFICIENCY vs. LOAD CURRENT WITH 1.8V INPUT
VOUT = 1.5V 90 EFFICIENCY (%)
MAX1955/56 toc03
100 VOUT = 1.8V 90 EFFICIENCY (%) VOUT = 2.5V
100 VOUT = 1.5V 90 EFFICIENCY (%) VOUT = 1.8V
100
80
VOUT = 1.5V VOUT = 1.2V
80 VOUT = 1.2V 70 VOUT = 1V
80 VOUT = 1.2V 70
70
60
60
60
50 0.1 1 10 100 LOAD CURRENT (A)
50 0.1 1 10 100 LOAD CURRENT (A)
50 0.1 1 10 100 LOAD CURRENT (A)
REFERENCE VOLTAGE vs. REFERENCE LOAD CURRENT
MAX1955/56 toc04
STEP-DOWN SWITCHING FREQUENCY vs. INPUT VOLTAGE
MAX1955/56 toc05
CHANGE IN OUTPUT VOLTAGE vs. LOAD CURRENT WITH 3.3V INPUT
VOUT = 1.8V CHANGE IN OUTPUT VOLTAGE (mV) 0 -2 -4 -6 -8 -10 -12 -14 0 OTHER OUTPUT SET TO 1.8V WITH 2.5A LOAD CURRENT 5 10 15 20 25 VOUT = 1.5V VOUT = 1.2V VOUT = 2.5V
MAX1955/56 toc06
1.290
640 630 620 FREQUENCY (kHz) 610 600 590 580 570 560 550 TA = +25C TA = -40C TA = +85C
2
REFERENCE VOLTAGE (V)
1.285
1.280
1.275
1.270 -50 -40 -30 -20 -10 0 10 20 30 40 50 REFERENCE LOAD CURRENT (A)
540 1.6 2.1 2.6 INPUT VOLTAGE (V) 3.1 3.6
LOAD CURRENT (A)
CHANGE IN OUTPUT VOLTAGE vs. LOAD CURRENT WITH 3.3V INPUT
MAX1955/56 toc07
OUTPUT VOLTAGE vs. INPUT VOLTAGE WITH NO LOAD
MAX1955/56 toc08
OUTPUT VOLTAGE vs. INPUT VOLTAGE WITH NO LOAD
VOUT = 2.5V 2.5 OUTPUT VOLTAGE (V) 2.0 1.5 1.0 VOUT = 1.2V 0.5 0 OTHER OUTPUT SET TO 1.8V WITH 25A LOAD CURRENT 2.35 2.60 2.85 3.10 3.35 3.60 DEVICE IN DROPOUT VOUT = 1.8V VOUT = 1.5V
MAX1955/56 toc09
2 VOUT = 2.5V CHANGE IN OUTPUT VOLTAGE (mV) 0 -2 -4 -6 -8 -10 -12 -14 0 5 10 15 20 OTHER OUTPUT SET TO 1.8V WITH 25A LOAD CURRENT VOUT = 1.5V VOUT = 1.2V VOUT = 1.8V
3.0 VOUT = 2.5V 2.5 OUTPUT VOLTAGE (V) 2.0 1.5 1.0 VOUT = 1.2V 0.5 0 OTHER OUTPUT SET TO 1.8V WITH 2.5A LOAD CURRENT 2.35 2.60 2.85 3.10 3.35 DEVICE IN DROPOUT VOUT = 1.8V VOUT = 1.5V
3.0
25
3.60
LOAD CURRENT (A)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
6
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1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers MAX1955/MAX1956
Typical Operating Characteristics (continued)
(Circuit of Figure 5, TA = +25C, unless otherwise noted.)
OUTPUT VOLTAGE vs. INPUT VOLTAGE WITH 25A LOAD
MAX1955/56 toc10
OUTPUT VOLTAGE vs. INPUT VOLTAGE WITH 25A LOAD
MAX1955/56 toc11
MAX1956 CHANGE IN OUTPUT VOLTAGE vs. INPUT VOLTAGE WITH NO LOAD
VOUT = 1.2V VOUT = 1V VOUT = 0.8V 0 -2 -4 -6 -8 -10 -12 -14 1.6 OTHER OUTPUT SET TO 1.8V WITH 2.5A LOAD CURRENT 2.1 2.6 INPUT VOLTAGE (V) 3.1 3.6
MAX1955/56 toc12
3.0 WITH 20A LOAD 2.5 OUTPUT VOLTAGE (V) 2.0 1.5 1.0 0.5 0 2.35 2.60 2.85 3.10 3.35 OTHER OUTPUT SET TO 1.8V WITH 2.5A LOAD CURRENT DEVICE IN DROPOUT VOUT = 1.8V VOUT = 1.5V VOUT = 2.5V
3.0 WITH 20A LOAD 2.5 OUTPUT VOLTAGE (V) 2.0 1.5 1.0 VOUT = 1.2V 0.5 0 OTHER OUTPUT SET TO 1.8V WITH 25A LOAD CURRENT 2.35 2.60 2.85 3.10 3.35 DEVICE IN DROPOUT VOUT = 1.8V VOUT = 1.5V VOUT = 2.5V
2 CHANGE IN OUTPUT VOLTAGE (mV)
VOUT = 1.2V
3.60
3.60
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
CHANGE IN OUTPUT VOLTAGE vs. INPUT VOLTAGE WITH NO LOAD
MAX1955/56 toc13
CHANGE IN OUTPUT VOLTAGE vs. INPUT VOLTAGE WITH 25A LOAD
MAX1955/56 toc14
CHANGE IN OUTPUT VOLTAGE vs. INPUT VOLTAGE WITH 25A LOAD
VOUT = 1.2V 0 -2 -4 -6 -8 -10 -12 -14 VOUT = 1V VOUT = 0.8V MAX1956 ONLY
MAX1955/56 toc15
2 CHANGE IN OUTPUT VOLTAGE (mV) 0 -2 -4 -6 -8 -10 -12 -14 1.60
VOUT = 1.2V
2 VOUT = 1.2V CHANGE IN OUTPUT VOLTAGE (mV) 0 -2 -4 -6 -8 -10 -12 -14 OTHER OUTPUT SET TO 1.8V WITH 2.5A LOAD CURRENT 1.60 2.10 2.35 2.60 INPUT VOLTAGE (V) 3.10 MAX1956 VOUT = 1V ONLY VOUT = 0.8V
2 CHANGE IN OUTPUT VOLTAGE (mV)
VOUT = 1V MAX1956 ONLY
VOUT = 0.8V
OTHER OUTPUT SET TO 1.8V WITH 25A LOAD CURRENT 2.10 2.35 2.60 INPUT VOLTAGE (V) 3.10 3.60
OTHER OUTPUT SET TO 1.8V WITH 25A LOAD CURRENT 1.60 2.10 2.35 2.60 INPUT VOLTAGE (V) 3.10 3.60
3.60
LOAD TRANSIENT WITH 1.5V OUTPUT
MAX1955/56 toc16
SWITCHING WAVEFORMS
MAX1955/56 toc17
SYNCHRONIZATION WAVEFORMS
MAX1955/56 toc18
50mV/div VOUT
VLX2
5V/div VSYNC 1V/div
IL2 VLX1
5A/div
5V/div
VDH1
5V/div
IOUT
10A/div
IL1
5A/div
VDH2
5V/div
10s/div
400ns/div
2s/div
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1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers MAX1955/MAX1956
Typical Operating Characteristics (continued)
(Circuit of Figure 5, TA = +25C, unless otherwise noted.)
NO LOAD TO SHORT CIRCUIT
MAX1955/56 toc19
20A LOAD TO SHORT CIRCUIT
MAX1955/56 toc20
HIGH OUTPUT MARGINING
MAX1955/56 toc21
VCTL1
5V/div
VOUT
1V/div
VOUT
1V/div
VCTL2
5V/div
IL 10A/div IL 10A/div 0A
VOUT1
100mV/div
VOUT2
100mV/div
40s/div
40s/div
100s/div
LOW-OUTPUT MARGINING
MAX1955/56 toc22
SHUTDOWN/STARTUP WITH SEQ = GND
MAX1955/56 toc23
SHUTDOWN/STARTUP WITH SEQ = AVDD
MAX1955/56 toc24
VCTL1
5V/div
VCTL1
5V/div VCTL1
5V/div
VCTL2
5V/div
VCTL2
5V/div VCTL2
5V/div
VOUT1
100mV/div
VOUT1
1V/div VOUT1
1V/div
VOUT2 100s/div
100mV/div
VOUT2 4ms/div
1V/div VOUT2 4ms/div
1V/div
Pin Description
PIN 1 2 3 4 NAME DL1 LX1 DH1 BST1 FUNCTION Low-Side MOSFET Gate-Driver Output. Connect to the low-side MOSFET gate. DL1 is pulled low in shutdown. Inductor Connection. Connect to the switched side of the inductor. High-Side MOSFET Gate-Driver Output. Connect to the high-side MOSFET gate. DH1 is pulled low in shutdown. High-Side MOSFET Gate-Driver Bootstrap Connection. Connect a capacitor from BST1 to LX1 and a Schottky diode from VDD to BST1. Frequency Synchronization Input. Connect to GND for normal 600kHz operation, or drive with a clock signal from 1080kHz to 1320kHz. The two step-down regulators are synchronized to alternating clock pulses, resulting in 180 out-of-phase operation at half the synchronization frequency.
5
SYNC
8
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1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers
Pin Description (continued)
PIN 6 NAME EN FUNCTION Enable and Voltage Margining Input. Connect EN to IN for normal operation or connect to GND for shutdown. Set VEN = (1/3)VIN to set the outputs to -4% of nominal. Set VEN = (2/3)VIN to set the outputs to +4% of nominal (see the Shutdown and Output Voltage Margining (EN) section). Current-Limit Adjust. Sets the threshold for current sensing across the low-side MOSFET's RDS(ON). Connect ILIM1 to AVDD for a 150mV threshold. For adjustable constant current or foldback current-limit setting, see the Current Limit section. Feedback Input. Connect to a voltage-divider from the output to GND to set the output voltage (see the Setting the Output Voltage section). Compensation. Internally pulled to ground during shutdown (see the Compensation Design section). Ground. Connect to the PC board analog ground plane. Connect PC board power ground plane and analog ground plane with a single connection. 1.28V Reference. Connect a 0.22F capacitor from REF to GND. Ground. Connect to the PC board analog ground plane. Connect the PC board power ground plane and analog ground plane with a single connection. Compensation. Internally pulled to ground during shutdown (see the Compensation Design section). Feedback Input. Connect to a voltage-divider from the output to GND to set the output voltage (see the Setting the Output Voltage section). Current-Limit Adjust. Sets the threshold for current sensing across the low-side MOSFET's RDS(ON). Connect ILIM2 to AVDD for a 150mV threshold. For adjustable constant current or foldback current-limit setting, see the Current Limit section. Analog Supply Input. Connect a 10 resistor from VDD to AVDD and a 0.47F capacitor from AVDD to GND. Power-Sequence Input. Connect SEQ to GND to set OUT1 and OUT2 to power up and power down simultaneously. Connect SEQ to IN to make OUT1 power up first and power down last. High-Side MOSFET Gate-Driver Bootstrap Connection. Connect a capacitor from BST2 to LX2 and a Schottky diode from VDD to BST2. High-Side MOSFET Gate-Driver Output. Connect to the high-side MOSFET gate. DH2 is pulled low in shutdown. Inductor Connection. Connect to the switched side of the inductor. Low-Side MOSFET Gate-Driver Output. Connect to the low-side MOSFET gate. DL2 is pulled low in shutdown. Power Ground. Connect to the low-side MOSFET source for regulator 2 and PC board power ground plane. Input Supply Internal Boost Regulator Output. Connect to VDD1, and bypass with a 10F capacitor to GND. Internal Boost Regulator Inductor Connection. Connect a 4.7H inductor from LXB to IN. Internally shorted to VDD2 in shutdown. Power Ground. Connect to PC board power ground plane. Internal Boost Regulator Output. Connect to VDD2. Power Ground. Connect to the low-side MOSFET source for regulator 1 and PC board power ground plane. Exposed Pad. Solder to the PC board analog ground plane for optimum power dissipation.
MAX1955/MAX1956
7
ILIM1
8 9 10 11 12 13 14
FB1 COMP1 GND1 REF GND COMP2 FB2
15 16 17 18 19 20 21 22 23 24 25 26 27 28 Exposed Pad
ILIM2 AVDD SEQ BST2 DH2 LX2 DL2 PGND2 IN VDD2 LXB PGND VDD1 PGND1 --
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1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers MAX1955/MAX1956
REF AVDD IN VDD2 1.28V BIAS UVLO BOOST CONTROL GND GND1 COMP1 FB1 SOFTSTART DAC EA PWM R S VOLTAGE MARGINING AND SHUTDOWN fSW SYNC (2 x fSW) OSCILLATOR fSW x0.15 5A Q Q LX1 VDD1 DL1 EN PGND1 CONVERTER 1 PGND BST1 DH1 CURRENT LIMIT AND SHUTDOWN LXB
SEQ
SEQUENCING 1V ILIM1
4V COMP2 CONVERTER 2 BST2 DH2 LX2 VDD2 DL2 PGND2 ILIM2
FB2
Figure 1. Functional Diagram
Detailed Description
The MAX1955/MAX1956 are dual-output, fixed-frequency, voltage-mode, PWM step-down controllers with 0.5% output accuracy. Each controller switches at a constant 600kHz and is 180 out-of-phase with the other controller, which reduces input ripple current and the number of input capacitors. Figure 1 is the functional diagram.
An on-chip step-up bias supply generates a 5V gate drive to deliver up to 25A output current per phase with low-cost N-channel MOSFETs at up to 93% efficiency. Lossless adjustable current limit eliminates expensive current-sense resistors and improves efficiency. Foldback current limit reduces power dissipation during short-circuit condition and handles transient overloads better than controllers using hiccup-mode short-circuit protection.
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1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers
Output voltage margining shifts the output voltage by 4% from the nominal value to simplify system testing. Outputs also can be powered up and down in selectable sequences to meet core and logic supply rail requirements. current-sense signal (measured from PGND_ to LX_) is above the current-limit threshold, the MAX1955/ MAX1956 do not initiate a new cycle, and COMP_ is pulled to ground. Since valley current sensing is used, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current (Figure 2). The exact current-limit characteristic and maximum load capacity are a function of the lowside MOSFET's on-resistance, the current-limit threshold, the inductor value, and the input voltage. This provides a robust lossless current sense that does not require current-sense resistors. An added feature is the implementation of Schottky diodes D3 and D4 (as shown in Figure 5), which reduce output short-circuit currents.
MAX1955/MAX1956
DC-to-DC PWM Controller
The MAX1955/MAX1956 step-down DC-to-DC converters use a PWM voltage-mode control scheme. The controller generates the clock signal by dividing down the internal oscillator (or SYNC signal when using an external clock) so that each controller's switching frequency equals 1/2 the oscillator frequency. An internal transconductance error amplifier produces an integrated error voltage at the COMP_ pin, providing high DC accuracy. The voltage at COMP sets the duty cycle, using a PWM comparator and a ramp generator. At the rising edge of the clock, Regulator 1's high-side N-channel MOSFET turns on and remains on until either the appropriate duty cycle or the maximum duty cycle is reached. Regulator 2 operates out of phase, so its high-side MOSFET turns on at the falling edge of the clock. During the on-time of each high-side MOSFET, the associated inductor current ramps up. During the second half of the switching cycle, the highside MOSFET turns off and the low-side N-channel MOSFET (synchronous rectifier) turns on. The inductor releases its stored energy as its current ramps down, providing current to the load.
Constant-Current Limit
The adjustable current limit accommodates MOSFETs with a wide range of on-resistance values. The currentlimit threshold is adjusted with an external resistor connected from ILIM_ to GND (RILIM_). The adjustment range is 75mV to 300mV, measured across the low-side MOSFET. The value of RILIM_ is calculated using the following formula: RILIM _ = IVALLEY x RDS(ON) 0.15 x 5A
High-Side Gate-Drive Supply (BST)
The gate-drive voltage for the high-side N-channel switch is generated by a flying capacitor. This capacitor between BST and LX is alternately charged from the VDD supply and placed in parallel to the high-side MOSFET's gate and source terminal through the high-side driver. On startup, the low-side MOSFET forces LX to ground and charges the boost capacitors to VDD through the Schottky diodes (D1 and D2 of Figure 5). On the second half cycle, the controller turns on the high-side MOSFET by closing an internal switch between BST and DH. This provides the necessary gate-to-source voltage to turn on the high-side MOSFET, an action that boosts the 5V gate-drive signal above the input voltage.
where IVALLEY is the valley current limit and RDS(ON) is the on-resistance of the low-side MOSFET. To avoid reaching the current limit at a lower current than expected, use the maximum value for RDS(ON) at an elevated junction temperature. Refer to the MOSFET manufacturer's data sheet for maximum values.
IPEAK
ILOAD INDUCTOR CURRENT
IVALLEY
Current Limit
The current-limit circuit employs a "valley" currentsensing algorithm that uses the on-resistance of the low-side MOSFET as a current-sensing element. If the
TIME
Figure 2. Inductor Current Waveform
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1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers MAX1955/MAX1956
Foldback Current Limit
Foldback current limit is used to reduce power dissipation during overload and short-circuit conditions. This is accomplished by lowering the current-limit threshold as the output voltage drops because of overload. To use foldback current limit, connect one resistor (RFOBK) from ILIM_ to the corresponding output, and connect another resistor (RILIM) from ILIM_ to GND. The values of RILIM and RFOBK are calculated as follows: 1) First, select the percentage of foldback (PFB). This percentage corresponds to the current limit when VOUT equals zero, divided by the current limit when VOUT equals its nominal voltage. Typical values are 15% to 30%. To solve for the resistor values, use the following equations: RFOBK = PFB x VOUT 5A(1 - PFB ) In this event, the main outputs and the internal boost regulator are disabled. The boost regulator starts up again once the voltage at IN rises above the UVLO threshold.
Startup and Output Sequencing
The MAX1955/MAX1956 use a digital soft-start to reduce input inrush current during startup. In soft-start, the output voltage is ramped up by increasing the FB_ regulation voltage in 80 steps of 10mV. Total soft-start time is typically 4.27ms. Some power supplies exhibit soft regulation during softstart. If the MAX1955/MAX1956 are powered from such a power supply and enabled at or before power-up, the input voltage might dip below the UVLO threshold, and the output might not soft-start properly. To avoid such issues, enable the MAX1955/MAX1956 after the input supply has stabilized or add an RC filter to the IN pin of the IC as shown in Figure 6. The value of R20 is ~510, and the value of capacitor C31 is from 1F to 10F, depending on the startup characteristic of the input power supply. The capacitor value is chosen to provide power to the IC (100A max) and keep it from falling below the UVLO threshold during the input powersupply dip. The outputs can be set to power up at the same time, or output 1 can be set to power up first and power down last. Connect SEQ to GND for simultaneous power up/down. Connect SEQ to IN to make output 1 power up first and power down last. Figure 3 is a timing diagram. If there is a fault condition (such as a short circuit) on output 1 causing its voltage to drop below 90% of its nominal regulation voltage, and SEQ is connected to IN, then output 2 shuts down. Once the fault is cleared, allowing the voltage on output 1 to rise above 90% of its nominal regulation voltage, output 2 soft-starts and powers up again.
RILIM =
6.67 x RDS(ON) x IVALLEY x (1- PFB ) x RFOBK VOUT - 6.67 x RDS(ON) x IVALLEY x (1- PFB )
(
)
2) Select PFB values that provide R ILIM greater than zero.
Recovery from Overload and Short Circuit
The MAX1955/MAX1956 do not recover to nominal output voltage at heavy load (near full load) after an overload or short-circuit condition, but they might operate at a voltage below the nominal output until the input power or EN pin is cycled through the OFF state. If automatic recovery is mandatory, without cycling EN or input power, add an RC filter of 1 and 0.015F at LX_'s pins, as shown in Figure 6. Doing so decreases the efficiency by 2% to 3%, depending on the input voltage, output voltage, and current.
AVDD Decoupling
Due to high switching frequency and tight output tolerance (0.5%), decoupling between VDD and AVDD is recommended. Connect a 10 resistor between VDD and AVDD and a 0.47F capacitor between AVDD and GND. Place the capacitor as close to AVDD as possible.
SEQ = GND EN OUT1 OUT2 4.27ms 4.27ms 4.27ms 4.27ms SEQ = IN
Undervoltage Lockout (UVLO)
When the voltage at IN drops below its undervoltage lockout (UVLO) threshold (see the Electrical Characteristics), the MAX1955/MAX1956 determine that the input supply voltage is too low to power the IC.
Figure 3. Timing Diagram
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1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers
Synchronization
An external clock of 1080kHz to 1320kHz at SYNC forces the controller to switch at half of this clock frequency. DH1 and DH2 positive-going edges alternately synchronize to the rising edge of the external clock, thus operating 180 out-of-phase with each other. See the Synchronization and Switching Waveforms in the Typical Operating Characteristics.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation of the MAX1955/MAX1956. When the junction temperature exceeds +160C, an internal thermal sensor shuts down the device, allowing the IC to cool. The thermal sensor turns the device on after the junction temperature cools by 15C. In a continuous thermaloverload condition, this results in a pulsed output.
MAX1955/MAX1956
Shutdown and Output Voltage Margining (EN)
The MAX1955/MAX1956 feature a low-power shutdown mode that reduces the IC's current consumption to less than 20A. For normal operation, connect EN to IN. To place the part in low-current shutdown mode, connect EN to GND. When the MAX1955/MAX1956 enter shutdown (EN goes low), soft-stop begins. In soft-stop, the output voltage is ramped down by lowering the FB_ regulation voltage to zero in 80 steps of 10mV. Total soft-stop time is typically 4.27ms. Each controller can be shut down individually by pulling COMP_ to GND with an open collector NPN transistor (Figure 6). This shuts down the controller immediately without going through soft-stop. Once COMP_ is released, the controller powers up without going through soft-start. To protect against inrush current when using this power-up/-down method, use foldback current limit. Also, connect SEQ to GND to prevent output 2 from powering down when the voltage on output 1 drops. In an effort to improve quality, many OEMs are testing their system's operation over the range of minimum and maximum supply voltage. To facilitate this testing, the MAX1955/MAX1956 have a voltage-margining feature that increases or decreases the output voltages by 4%. The voltage on EN controls voltage margining. To increase the output voltage by 4%, apply (2/3) VIN to EN. To reduce the output voltage by 4%, apply (1/3) VIN to EN. One easy way to use the voltage-margining feature is to make two control logic inputs (CTL1 and CTL2) by connecting two resistors to EN. Connect a 200k resistor from EN to CTL1, and a 100k resistor from EN to CTL2 (Figure 5). The voltage margining is then controlled by connecting CTL1 and CTL2 to IN or GND, as shown in Table 1. Before applying voltage-margining, pull VCTL1 and VCTL2 to > VIN - 0.5V to ensure proper startup.
Low-Side MOSFET NegativeCurrent Conduction
Under most operating conditions, the low-side MOSFET conducts only positive inductor currents that flow from source to drain and 1/2 of the inductor peak-to-peak ripple current (~15% full load current) in the negative direction when output is at no load. If the MAX1955/ MAX1956 are disabled before their soft-start cycle is complete (~4ms), the converter is disabled without a soft-stop, and the output discharges through its load. In this case, if the converter is reenabled before the output capacitor discharges completely, the soft-start cycle resets the reference input to the error amp to zero and ramps up again. The converter forces DL on until the feedback drops below the reference input. If the output is almost fully charged when the converter turns back on, a large negative current can build up in the inductor. If the negative current is excessive, a high LX voltage spike can occur because of parasitic circuit inductances as DL is released. This high LX voltage spike can shut down and latch off the circuit. To prevent this from happening, add a series resistor between DL and the gate of the low-side MOSFET (Figure 6) to slow down the turn-off di/dt, reducing the voltage spike and preventing the circuit from shutting down. A 1 resistor works fine for most applications without noticeable degrading impact on efficiency or Cdv/dt-induced turn-on effect.
Table 1. Voltage Margining
CTL1 VIN 0 VIN 0 CTL2 VIN VIN 0 0 EN VIN (2/3)VIN (1/3)VIN 0 OUTPUT Nominal +4% -4% Shutdown
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13
1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers MAX1955/MAX1956
Design Procedure
Setting the Output Voltage
Output voltage is set with a resistor-divider, as shown in Figure 4. The output voltage can be set to as low as 0.8V. The maximum output voltage is limited by maximum duty cycle and external component selection. Select RX (the resistor from FB to GND) between 8k and 10k, and calculate RY from: V RY = RX x OUT - 1 0.8
RY RC COMP_ CF RX Cc VOUT_
FB_
Figure 4. Feedback Divider Network and Compensation Circuitry
Inductor Selection
Three key inductor parameters must be specified for operation with the MAX1955/MAX1956: inductance value (L), peak inductor current (IPEAK), and DC resistance (RDC). A good compromise between size and efficiency is to set the inductor peak-to-peak ripple current equal to 30% of maximum load current, thus LIR = 0.3. The switching frequency, input voltage, output voltage, and selected LIR determine the inductor value as follows: L= VOUT (VIN - VOUT ) VIN x fSW x IOUT(MAX) x LIR
Input Capacitor Selection
The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit's switching. The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents defined by the following equation:
IRMS =
1 VIN
(IOUT1 )2 x VOUT1 x (VIN - VOUT1) + (IOUT2 )2
x VOUT2 x (VIN - VOUT2 )
where fSW is the switching frequency (typically 600kHz). The exact inductor value is not critical and can be adjusted in order to make trade-offs among size, cost, and efficiency. Lower inductor values minimize size and cost, and also improve transient response, but reduce efficiency and increase output voltage ripple because of higher peak currents. Higher inductance increases efficiency by reducing the RMS current. However, resistive losses because of extra wire turns could exceed the benefit gained from lower AC current levels, especially when the inductance is increased without also allowing larger inductor dimensions. Find a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. The inductor's saturation current rating must exceed the peak inductor current at the maximum defined load current (ILOAD(MAX)): LIR IPEAK = IOUT(MAX) + xI 2 OUT(MAX)
Output Capacitor Selection
The key selection parameters for the output capacitor are the actual capacitance value, the ESR, the ESL, and the voltage-rating requirements, which affect the overall stability, output ripple voltage, and transient response. The output ripple has three components: variations in the charge stored in the output capacitor, the voltage drop across the capacitor's ESR, and the voltage drop across the capacitor's ESL caused by the current into and out of the capacitor: VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C) + VRIPPLE(ESL) The output voltage ripple from the ESR is: VRIPPLE(ESR) = IP-P ESR The output voltage ripple because of the output capacitance is: VRIPPLE(C) = IP-P 8 x COUT x fSW
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1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers
The output voltage ripple due to the ESL of the output capacitor is: ESL VRIPPLE (ESL) = VIN ESL + L IP-P is the peak-to-peak inductor current: V -V V IP-P = IN OUT x OUT fSW x L VIN These equations are suitable for initial capacitor selection to meet the ripple requirement, but final values can depend on the relationship between the LC double-pole frequency and the capacitor ESR zero. Generally, the ESR zero is higher than the LC double pole. However, it is preferable to keep the ESR zero as close to the LC double pole as possible to negate the sharp phase shift of the typically high-Q double-LC pole (see the Compensation Design section). Solid polymer electrolytic capacitors are recommended because of their low ESR and ESL at the switching frequency. Higher output-current applications require multiple output capacitors connected in parallel to meet the output ripple voltage requirements. The response to a load transient depends on the output capacitor. After a load transient, the output voltage instantly changes by ESR x ILOAD + ESL x dI/dt. Before the controller can respond, the output deviates further, depending on the inductor and output capacitor values. After a short time (see the Typical Operating Characteristics), the controller responds by regulating the output voltage back to its nominal state. The response time depends on the closed-loop bandwidth. With a higher bandwidth, the response is faster, thus preventing the output voltage from deviating further from its nominal value. Do not exceed the capacitor's voltage or ripple-current ratings. loss equal to switching loss at nominal input voltage and maximum output current (see below). For low-side MOSFET, make sure that it does not spuriously turn on because of dV/dt caused by high-side MOSFET turning on, as this would result in shoot-through current degrading the efficiency. MOSFETs with a lower QGDto-QGS ratio have higher immunity to dV/dt. For proper thermal-management design, calculate the power dissipation at the desired maximum operating junction temperature, maximum output current, and worst-case input voltage (for low-side MOSFET, worst case is at VIN(MAX); for high-side MOSFET, it could be either at VIN(MIN) or VIN(MAX)). High-side MOSFET and low-side MOSFET have different loss components due to the circuit operation. Low-side MOSFET operates as a zero voltage switch; therefore, major losses are: the channel conduction loss (P LSCC), the bodydiode conduction loss (PLSDC), and the gate-drive loss (PLSDR): V 2 PLSCC = 1- OUT x (ILOAD ) x RDS(ON) VIN Use RDS(ON) at TJ(MAX): PLSDC = 2 ILOAD x VF x t DT x fSW where VF is the body-diode forward-voltage drop, tDT is the dead time (~25ns), and fSW is the switching frequency. Because of the zero-voltage switch operation, low-side MOSFET gate-drive loss occurs as a result of charging and discharging the input capacitance, (C ISS). This loss is distributed among the average DL gate driver's pullup and pulldown resistance, (RDL (0.68 typ)), and the internal gate resistance (RGATE) of the MOSFET (~2). The drive power dissipated is given by: RGATE 2 PLSDR = CISS x (VGS ) x fSW x RGATE + RDL High-side MOSFET operates as a duty-cycle control switch and has the following major losses: the channel conduction loss (PHSCC), the VI overlapping switching loss (PHSSW), and the drive loss (PHSDR). High-side MOSFET does not have body-diode conduction loss because the diode never conducts current: V 2 PHSCC = OUT x (ILOAD ) x RDS(ON) VIN
MAX1955/MAX1956
MOSFET Selection
The MAX1955/MAX1956 drive external, logic-level, Nchannel MOSFETs as the circuit-switch elements. The key selection parameters: On-resistance (RDS(ON)): the lower the better. Maximum drain-to-source voltage (VDSS): should be at least 20% higher than input supply rail at the highside MOSFET's drain. Gate charges (QG, QGD, QGS): the lower the better. Choose the MOSFETs with rated RDS(ON) at V GS = 4.5V. For a good compromise between efficiency and cost, choose the high-side MOSFET that has a conduction
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15
MAX1955/MAX1956
1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers
Figure 5. Typical Application Circuit
C1 10F L3 4.7H R1 1 C20 0.47F 4 BST1 DH2 LX2 R15 1 U1 R5 1 1 DL1 FB2 14 D4 R8 18k C26 33pF REF GND EN GND1 ILIM1 15 7 SYNC ILIM2 SEQ AVDD 16 10 12 C27 0.22F R11 60.4k R12 56.2k R13 10 C21 0.47F VDD 11 R18 75k OUT1 C23 6800pF R6 8.06k R19 90.9k C7 82pF PGND PGND1 PGND2 FB1 COMP1 COMP2 13 N4 26 28 D3 8 9 C24 6800pF R7 15k 6 5 R14 100k 17 C25 33pF 22 N3 MAX1955 C16 4700pF C8 82pF N7 N8 C14 4700pF DL2 21 R4 10k 20 DH1 LX1 19 3 N2 2 L1 0.3H N1 C9 0.47F L2 0.3H C12 680F C13 680F C17 4700pF N5 N6 C15 4700pF 1.8V 25A OUT2 D1 D2 23 27 24 IN VDD1 VDD2 25 18 LXB BST2 R16 1 C2 10F C3 10F VDD C4 10F C5 10F C6 10F R2 7.15k C22 10F
16
2.25V TO 3.6V
IN
C28 470F
C29 470F
1.5V 25A
OUT1
C10 680F
C11 680F
R3 8.06k
R9 200k
CTL1
R10 100k
CTL2
SYNC
______________________________________________________________________________________
SEQ
2.25V TO 3.6V C1 10F L3 4.7H 25 4 BST1 DH2 LX2 R15 1 R4 10k N8 C14 4700pF 20 C12 680F DH1 LX1 U1 N7 1 DL1 FB2 D4 R8 18k C26 33pF REF GND EN GND1 ILIM1 15 7 SYNC 10 12 C27 0.22F R11 60.4k R12 56.2k R13 10 AVDD 16 C21 0.47F R27 10k OFF Q1 MMBT3904 ON ENABLE2 R28 10k Q2 MMBT3904 VDD 11 R18 75k OUT1 C23 6800pF R6 8.06k R19 90.9k C7 82pF 14 PGND PGND1 PGND2 FB1 COMP1 COMP2 13 26 28 D3 8 9 C24 6800pF R7 15k 6 5 C25 33pF 22 MAX1955 R24 1 DL2 21 19 3 N2 2 L1 0.3H R5 1 C16 4700pF N4 N3 C8 82pF R23 1 C32 0.015F N1 R21 1 R22 1 C30 0.015F C9 0.47F L2 0.3H C13 680F N5 N6 C15 4700pF 1.8V 25A OUT2 R1 1 C20 0.47F C17 4700pF C31 4.7F D1 D2 23 27 24 IN VDD1 VDD2 18 LXB BST2 R16 1 C5 10F C6 10F C2 10F C3 10F R20 510 VDD C4 10F
IN
Figure 6. Independent Output On/Off Control
R2 7.15k 17 SEQ ILIM2 C22 10F OFF ON ENABLE1 R26 10k R25 10k
C28 470F
C29 470F
1.5V 25A
OUT1
C10 680F
C11 680F
R3 8.06k
R9 200k
CTL1
R10 100k
CTL2
SYNC
MAX1955/MAX1956
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R14 100k
1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers
17
1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers MAX1955/MAX1956
Use RDS(ON) at TJ(MAX). QGS + QGd PHSSW = VIN x ILOAD x fSW x IGATE where IGATE is the average DH driver output-current determined by: IGATE(ON) = 2.5 RDH + RGATE LPAR = 1
(2fR )
2
x CPAR
where RDH is the high-side MOSFET driver's on-resistance (1 typical) and RGATE is the internal gate resistance of the MOSFET (~2): RGATE PHSDR = QG x VGS x fSW x RGATE + RDH where VGS = VVDD = 5V. In addition to the losses above, allow about 20% more for additional losses because of MOSFET output capacitances and low-side MOSFET body-diode reverse recovery charge dissipated in the high-side MOSFET that is not well defined in the MOSFET data sheet. Refer to the MOSFET data sheet for thermal-resistance specifications to calculate the PC board area needed to maintain the desired maximum operating junction temperature with the above-calculated power dissipations. To reduce EMI caused by switching noise, add a 0.1F ceramic capacitor from the high-side switch drain to the low-side switch source, or add resistors in series with DH and DL to slow down the switching transitions. Adding series resistors increases the power dissipation of the MOSFET, so ensure that this does not overheat the MOSFET.
The resistor for critical dampening (RSNUB) is equal to 2 x fR x LPAR. Adjust the resistor value up or down to tailor the desired damping and the peak voltage excursion. The capacitor (CSNUB) should be at least 2 to 4 times the value of the C PAR in order to be effective. The power loss of the snubber circuit is dissipated in the resistor (PRSNUB) and can be calculated as: PRSNUB = CSNUB x ( VIN )
2
x fSW
where VIN is the input voltage and fSW is the switching frequency. Choose an RSNUB power rating that meets the specific application's derating rule for the power dissipation calculated.
Boost-Supply Diode and Capacitor
A low-current Schottky diode, such as CMSSH-3 from Central Semiconductor, works well for most applications. Do not use large-power diodes, because higher junction capacitance can charge up the BST to LX voltage and can exceed the device rating of 6V. The boost capacitor should be 0.1F to 4.7F, depending on the input and output voltages, external components, and PC board layout. The boost capacitance should be as large as possible to prevent it from charging to excessive voltage, but small enough to adequately charge during the minimum low-side MOSFET conduction time, which happens at maximum operating duty cycle (this occurs at minimum input voltage). In addition, ensure that the boost capacitor does not discharge to below the minimum gate-to-source voltage required to keep the high-side MOSFET fully enhanced for lowest on-resistance. This minimum gateto-source voltage VGS(MIN) is determined by: VGS(MIN) = VVDD QG CBOOST
MOSFET Snubber Circuit
Fast switching transitions cause ringing because of resonating circuit parasitic inductance and capacitance at the switching nodes. This high-frequency ringing occurs at LX's rising and falling transitions and can interfere with circuit performance and generate EMI. To dampen this ringing, a series R-C snubber circuit is added across each switch. Below is the procedure for selecting the value of the series R-C circuit: 1) Connect a scope probe to measure VLX to GND, and observe the ringing frequency, fR. 2) Find the capacitor value (connected from LX to GND) that reduces the ringing frequency by half. The circuit parasitic capacitance (CPAR) at LX is then equal to 1/3 the value of the added capacitance above. The circuit parasitic inductance (LPAR) is calculated by:
18
where VVDD is 5V, QG is the total gate charge of the high-side MOSFET, and CBOOST is the boost capacitor value.
Compensation Design
The MAX1955/MAX1956 use a voltage-mode control scheme that regulates the output voltage by comparing the error amplifier output (COMP) with a fixed internal ramp to produce the required duty cycle. The inductor and output capacitor create a double pole at the resonant frequency, which has a gain drop of 40dB per decade and phase shift of 180. The error amplifier
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1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers
must compensate for this gain drop and phase shift in order to achieve a stable high-bandwidth closed-loop system. The basic regulator loop consists of a power modulator, an output feedback divider, and an error amplifier. The power modulator has DC gain set by VIN/VRAMP, with a double pole set by the inductor and output capacitor and a single zero set by the output capacitor (COUT) and its ESR. Equations that define the power modulator follow: The DC gain of the power modulator: GMOD(DC) = VIN VRAMP pensation capacitor (CC), the amplifier-output resistance (RO 5M), and the compensation resistor (RC): fPEA = 1 2 x CC x (RO + RC )
MAX1955/MAX1956
A zero is set by the compensation resistor and the compensation capacitor: fZEA = 1 2 x CC x RC
where V RAMP = 1V. The double-pole frequency because of the inductor and output capacitor is: fPMOD = 1 2 LCOUT
The total closed-loop gain must equal unity at the crossover frequency, where the crossover frequency should be higher than fZESR, so that the -1 slope is used to cross over at unity gain. Also, the crossover frequency should be less than or equal to 1/5 the switching frequency: f fZESR < fC < SW 5 The loop-gain equation at the crossover frequency is: VFB x GEA ( fc) x GMOD( fc) = 1 VOUT where: GEA(fc) = gmEA RC, and GMOD(fc) = GMOD(DC) (fPMOD)2 / (fESR fC) The compensation resistor (RC) is calculated from: RC = VOUT gmEA x VFB x GMOD( fc)
The zero frequency because of the output capacitor's ESR is: fZESR = 1 2 x ESR x COUT
The output capacitor is usually composed of several same-value capacitors connected in parallel. With n capacitors in parallel, the output capacitance is: COUT = n x CEACH The total ESR is: ESR = ESREACH n
where gmEA = 2mS. Because of the underdamped (Q > 1) nature of the output LC double pole, the error amplifier compensation zero should be approximately 0.2 fPMOD to provide good phase boost. CC is calculated from: CC = 5 2 x RC x fPMOD
The ESR zero (f ZESR ) for a parallel combination of capacitors is the same as that of an individual capacitor. The feedback divider has a gain of GFB = VFB/VOUT, where VFB is 0.8V. The transconductance error amplifier has DC gain GEA(dc) of 80dB. A dominant pole is set by the com-
A small capacitor (CF) also can be added from COMP to GND to provide high-frequency decoupling. CF adds
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1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers MAX1955/MAX1956
another high-frequency pole (fPHF) to the error-amplifier response. This pole should be greater than 100 times the error-amplifier zero frequency in order to have negligible impact on the phase margin. This pole also should be less than half the switching frequency for effective decoupling: 100fZEA < fPHF < 0.5fSW Select a value for fPHF in the range given above, and then solve for CF using the following equation: CF = 1 2 x RC x fPHF
fZESR = 1 1 = 2 x COUT x ESR 2 x 1360 x 10-6 x 0.004 = 29.3kHz
Pick the crossover frequency (fC) in the range fZESR < fC < fSW/5: 29.3kHz < fC < 120kHz Select fC = 100kHz (this meets the criteria above), and the bandwidth is high enough for good transient response. The power-modulator gain at fC is: GMOD(fc) = = VIN VRAMP x (fPMOD )2 fZESR x fC
With two converters in proximity, there is a potential for crosstalk between the converters. Crosstalk can be managed by board layout and high-frequency filtering, which can be inserted by adding a high-frequency pole in the feedback network. To do so and minimize effect on phase margin, add capacitors C7 and C8 (Figure 5) with a pole frequency of: fPFB2 = (R4 + R6) / 2 x R4 x R6 x C7) fPFB1 = (R2 + R3) / (2 x R2 x R3 x C8) Set the poles above ~4 to 5 times the crossover frequency. Below is a numerical example to calculate the compensation values used in the typical application circuit of Figure 5: VIN = 3V (the midpoint of the input voltage range) VRAMP = 1V VOUT = 1.8V VFB = 0.8V IOUT(MAX) = 25A COUT = 2 x 680F ESR = 0.008 / 2 = 0.004 L = 0.3H gmEA = 2mS fSW = 600kHz
fPMOD = = 1 2 x L x COUT 1 2 x 0.3 x 10-6 x 1360 x 10-6 = 7.879kHz
(7.879kHz)2 3 x = 0.0477 1 29.3kHz x 100kHz
Pick RX = 8.06k, then RY = 10k (see the Setting the Output Voltage section). RC = VOUT gmEA x GMOD( fc) x VFB 1.8 = = 17.6k 0.002 x 0.8 x .0636
Select RC = 18k (nearest standard resistor value).
CC = 5 5 = = 5620pF 2 x RC x fPMOD 2 x 18k x 7.879kHz
Select CC = 6800pF (rounded up to the next standard capacitor value). Select fPHF in the range 100fZEA < fPHF < 0.5fSW. Hence: 157.6kHz < fPHF < 300kHz Select fPHF = 250kHz, and then solve for CF:
CF = 1 1 = = 33pF 2 x RC x fPHF 2 x 18k x 250kHz
A summary of feedback divider and compensation components follows: RX = 8.06k RY = 10k RC = 18k CC = 6800pF CF = 33pF
20
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1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers
Applications Information
PC Board Layout Guidelines
Careful PC board layout is important in any switching regulator. The switching power stage requires particular attention. Follow these guidelines for good PC board layout: 1) Place decoupling capacitors as close as possible to the IC pins. 2) Keep a separate power ground plane (connect to the sources of the low-side MOSFETs, the input and output capacitors, and PGND_ pins). Connect the input decoupling capacitors across the drain of the high-side MOSFETs and the source of the low-side MOSFETs. The signal ground plane (connected to the GND pin) is connected to the power ground plane at a single point. Keep the high-current paths as short as possible. 3) Connect the drains of the MOSFETs to a large land area to help cooling the devices to further improve efficiency and long-term reliability. 4) Ensure all feedback connections are short and direct. Place the feedback resistors as close to the IC as possible. 5) Route high-speed switching nodes (LX_) away from sensitive analog areas (FB_, COMP_). For a sample PC board layout, refer to the MAX1955 evaluation kit. Table 2 lists typical application circuit components.
PGND1 PGND VDD1 VDD2 LXB
Pin Configuration
TOP VIEW
PGND2
MAX1955/MAX1956
28
27
26
25
24
23
IN
DL1 LX1 DH1 BST1 SYNC EN ILIM1
1 2 3 4 5 6 7 10 11 12 13 14 8 9
22 21 20 19
DL2 LX2 DH2 BST2 SEQ AVDD ILIM2
MAX1955 MAX1956
18 17 16 15
FB1
REF
COMP1
GND1
GND
THIN QFN
Table 2. Typical Application Circuit Components
DESIGNATION C10-C13 C28, C29 D1-D4 L1, L2 L3 N1, N2, N5, N6 N3, N4, N7, N8 QTY 4 2 4 2 1 4 4 DESCRIPTION 680F, 2.5V POSCAPs Sanyo 2R5TPD680M8 470F, 6.3V POSCAPs Sanyo 6TPB470M Schottky diodes (SOT 323) Central CMSSH-3 0.3H, 35A inductors Sumida CDEP125(U)-0R3 4.7H inductor TDK LDR655312T-4R7W N-channel MOSFETs Vishay Si7892DP N-channel MOSFETs Vishay Si4842DY
Chip Information
TRANSISTOR COUNT: 8694 PROCESS: BiCMOS
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COMP2
FB2
21
1.6V to 5.5V Input, 0.5% Accurate, Dual 180 Out-of-Phase Step-Down Controllers MAX1955/MAX1956
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN.EPS
L
REV.
0.15 C A
D2
C L
D
b D2/2
0.10 M C A B
PIN # 1 I.D.
D/2
0.15 C B
k
PIN # 1 I.D. 0.35x45
E/2 E2/2 E (NE-1) X e
C L
E2
k L
DETAIL A
e (ND-1) X e
C L
C L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO.
21-0140
C
1 2
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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